1. Field of the Invention
The present invention relates to a synchronous semiconductor integrated circuit device that operates in synchronization with a clock signal, and particularly to the structure of a clock reproduction circuit that receives an external clock signal and generates an internal clock signal in synchronization with the external clock signal. More specifically, the present invention relates to the structure of generating speedily an internal clock signal in synchronization with an external clock signal even when the operating environment of the semiconductor integrated circuit device is varied.
Further specifically, the present invention relates to the structure of clock generation circuitry generating an internal clock signal speedily in synchronization with an external clock signal when the power is turned on or when a power down mode is released.
2. Description of the Background Art
In recent years, a clock synchronous semiconductor memory device that receives an external signal and data input/output in synchronization with a clock signal, such as a system clock, has been widely used. It is not necessary to take into account the skew between a control signal and an address signal since an externally applied clock signal is used as the timing reference. It is also not necessary to take the timing margin into account since the internal signal is generated in synchronization with the clock signal. Accordingly, the timing of initiating an internal operation can be advanced to allow high speed access.
The externally applied clock signal determines the data transfer rate since data input/output is carried out in synchronization with this external clock signal. Therefore, data transfer between an external processing device such as a microprocessor and a synchronous semiconductor memory device can be effected at high speed. The problem of degradation in the system performance due to increase in the waiting time of the microprocessor caused by the difference in the operating speed between the microprocessor and the main memory, such as a standard DRAM (Dynamic Random Access Memory), can be eliminated.
FIG. 82 is a schematic diagram of an entire structure of a conventional synchronous semiconductor memory device. In FIG. 82, the structure of a synchronous DRAM (Dynamic Random Access Memory) that operates in synchronization with an externally applied clock signal CLKex is presented as a synchronous semiconductor memory device.
Referring to FIG. 82, the synchronous semiconductor memory device includes an internal clock generation circuit 5000 receiving an external clock signal CLKex to generate an internal clock signal CLKin in synchronization with external clock signal CLKex, a memory circuit 5002 including a plurality of memory cells and a memory cell select circuit, an input buffer 5004 receiving an externally applied command CMD and a clock enable signal CKE in synchronization with internal clock signal CLKin, a command decode circuit 5006 identifying an operation mode specified according to an internal signal from input buffer 5004 to generate a signal designating the specified operation mode, a control circuit 5008 generating a control signal required for the specified operation according to the operation mode designating signal from command decode circuit 5006, and an address input circuit 5010 receiving an externally applied address signal ADD in synchronization with internal clock signal CLKin and latching the input address signal according to a control signal from control circuit 5008 to generate an internal address signal.
Command CMD applied to input buffer 5004 includes a plurality of control signals, i.e., a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE. A combination of the states of these control signals at the rising edge of internal clock signal CLKin provides a command. Under control of control circuit 5008, address input circuit 5010 latches a row address signal specifying a memory cell row in memory circuit 5002 and a column address signal specifying a memory cell column in memory circuit 5002 to generate internal row and column address signals. The generated internal row and column address signals are applied to memory circuit 5002.
Memory circuit 5002 includes an array with a plurality of memory cells arranged in rows and columns and, memory cell array peripheral circuitry including a row decode circuit decoding a row address signal to select the addressed row, a column decode circuit decoding a column address signal to select the addressed column, and a sense amplifier to sense, amplify and latch the data of the memory cell connected to the selected row.
The synchronous semiconductor memory device further includes a write/read circuit 5012 to carry out data writing/reading with respect to a selected memory cell in memory circuit 5002 under control of control circuit 5008, an input/output circuit 5014 operating under control of control circuit 5008 to transfer data between write/read circuit 5012 and an external device, and an internal power supply voltage generation circuit 5016 generating internal power supply voltages Vccp and Vcca from an external power supply voltage Vex.
Control circuit 5008 generates various control signals in synchronization with internal clock signal CLKin according to the operation mode designating signal from command decode circuit 5006. Write/read circuit 5012 includes a preamplifier to amplify data read out from a selected memory cell, a write drive circuit to write data into a selected memory cell, and a transfer circuit to transfer the data in synchronization with internal clock signal CLKin. Input/output circuit 5014 includes an input circuit generating internal write data from externally applied data DQ in a data write operation, and an output circuit buffering the data read out from write/read circuit 5012 to generate external read data in a data read out operation.
Internal power supply voltage generation circuit 5016 down-converts external power supply voltage Vex to generate internal power supply voltages Vccp and Vcca. Power supply voltage Vccp is applied to internal clock generation circuit 5000, input buffer 5004, command decode circuit 5006, control circuit 5008, address input circuit 5010, write/read circuit 5012, input/output circuit 5014, and the peripheral circuitry included in memory circuit 5002. More specifically, internal power supply voltage Vccp from internal power supply voltage generation circuit 5016 is applied as an operating power supply voltage in common to the peripheral circuits. Internal power supply voltage Vcca is applied to the memory cell array in memory circuit 5002 (specifically, employed as a sense amplifier drive power supply voltage).
An external power supply voltage VDDQ dedicated for data output is applied to the final stage output buffer circuit in input/output circuit 5014. By applying the output-dedicated power supply voltage VDDQ to input/output circuit 5014, internal power supply voltages Vccp and Vcca maintain their voltage levels even in the case where an output terminal is driven by a great drivability to result in great current consumption during data output. The internal circuitry can be operated stably without the influence of variation in the power supply voltage during data output.
By generating independently an internal power supply voltage Vcca for the array and internal power supply voltage Vccp for the peripheral circuitry, power supply voltage Vccp directed to the peripheral circuitry can be maintained stably at the required voltage level even when a relatively large current is consumed during a sense amplifier operation in memory circuit 5002. The power supply voltage applied to the memory cell of the memory array is set at the optimum value. The breakdown voltage of an insulated gate type field type effect transistor (MOS transistor) which is a component of a memory cell can be ensured.
Clock enable signal CKE controls generation of internal clock signal CLKin. When clock enable signal CKE attains an inactive state of an L level (logical low), generation of internal clock signal CLKin is stopped at the next clock cycle. In a power down mode, a power down mode designating signal PD from control circuit 5008 is applied to internal clock generation circuit 5000, whereby generation of internal clock signal CLKin in internal clock generation circuit 5000 is stopped. In the synchronous semiconductor memory device, the internal circuit operates in synchronization with internal clock signal CLKin. Inhibition of generation of internal clock signal CLKin causes the operation of the internal circuit to be halted. The charging/discharging operation of signal lines is halted, so that current consumption is reduced. This operation mode of reducing current consumption by inhibiting generation of the internal clock signal to stop operation of internal circuitry is referred to as a "power down mode".
When clock enable signal CKE attains an L level or when the power down mode is specified by a particular command, input buffer 5004 and the buffer circuits of address input circuit 5010 have their operation stopped. Therefore, the output signals of the buffer circuits are maintained at the low voltage level.
Internal clock generation circuit 5000 is generally formed of a PLL (phase locked loop) circuit or a DLL (delayed locked loop) circuit to generate an internal clock signal CLKin phase-locking with external clock signal CLKex. When a general buffer circuit is employed as internal clock generation circuit 5000, the gate delay in the buffer circuit becomes too great for a high speed clock signal. Therefore, internal circuitry cannot be operated at high speed. By generating an internal clock signal using such a phase synchronization circuit, it is intended to implement proper input of an external signal and proper data input/output even with a high speed clock signal through generation of an internal clock signal phase-locking with an external clock signal.
FIG. 83 schematically shows a structure of the portion for generating a periphery power supply voltage Vccp included in internal power supply voltage generation circuit 5016 of FIG. 82. Referring to FIG. 83, internal power supply voltage generation circuit 5016 includes an active voltage-down converter rendered active in response to an internal circuit activation signal .phi.ACT to generate a periphery power supply voltage Vccp from external power supply voltage Vex, and a standby voltage-down converter 5016s constantly operating to generate periphery power supply voltage Vccp from external power supply voltage Vex. When peripheral circuitry is inactive, standby voltage-down converter 5016s prevents the voltage level of periphery power supply voltage Vccp from being reduced by a leakage current and the like. Active voltage-down converter 5016a is rendered active in response to activation of internal circuit activation signal .phi.ACT for compensating for current consumption during operation of peripheral circuitry with a great drivability to maintain periphery power supply voltage Vccp at a constant level.
Standby voltage-down converter 5016s includes a comparator 5016sa comparing a reference voltage Vref and periphery power supply voltage Vccp, and a current drive transistor 5016sb supplying current from an external power supply node to an internal power supply line according to the signal output from comparator 5016sa. The current drivability of current drive transistor 5016sb is set at a low level.
Active voltage-down converter 5016a includes a comparison circuit 5016aa rendered active in response to activation of internal circuit activation signal .phi.ACT to compare periphery power supply voltage Vccp with reference voltage Vref, and a current drive transistor 5016ab supplying current from an external power supply node to an internal power supply line according to the signal output from comparison circuit 5016aa. The current drivability of current drive transistor 5016ab is set to a relatively great level. Comparison circuit 5016aa includes a comparator CMP comparing reference voltage Vref with periphery power supply voltage Vccp, and a current source transistor ATr rendered conductive in response to internal circuit activation signal .phi.ACT to form an operating current path for comparator CMP to activate comparator CMP.
According to the structure of internal power supply voltage generation circuit 5016a of FIG. 83, comparator 5016sa outputs a signal of an H level (logical high) when periphery power supply voltage Vccp is higher than reference voltage Vref, to maintain current drive transistor 5016sp at a nonconducting state. When reference voltage Vref is higher than periphery power supply voltage Vccp, comparator 5016sa provides a low level signal according to the difference. The conductance of current drive transistor 5016sb is increased, whereby current is supplied from the external power supply node to the internal power supply line. Active voltage-down converter 5016a operates in a manner similar to that of standby voltage-down converter 5016s when internal circuit activation signal .phi.ACT is active. Therefore, periphery power supply voltage Vccp is maintained at a level substantially equal to that of reference voltage Vref.
The reason why periphery power supply voltage Vccp and array power supply voltage Vcca are generated independently is set forth in the following. Due to difference in voltage level between array power supply voltage Vcca and periphery power supply voltage Vccp, peripheral circuitry is operated at high speed while the breakdown voltage of the memory cell in the array is ensured. The sense amplifier circuit that consumes array power supply voltage Vcca consumes a relatively large current during operation thereof. However, high speed response is not required for the circuit that generates the power supply voltage for the sense amplifier circuit. In contrast, high speed response is required for the circuit that generates periphery power supply voltage Vccp in order to transmit the control signals and data speedily. Thus, array power supply voltage Vcca and periphery power supply voltage Vccp are generated individually from different voltage-down converters to satisfy respective requirements.
When the circuit scale of the semiconductor integrated circuit becomes larger and the number of bits of data transmitted internally increases, the number of circuit portions that operate simultaneously becomes greater to result in greater power consumption. Variation in periphery power supply voltage Vccp causes variation in the operating speed of internal clock generation circuit 5000 since this periphery power supply voltage Vccp is also consumed by internal clock generation circuit 5000. Internal clock generation circuit 5000 generally includes a train of inverters. The phases of external clock signal CLKex and internal clock signal CLKin are synchronized by adjusting the operating current of the train of inverters. However, variation in periphery power supply voltage Vccp causes variation in the operating characteristic of the inverters in internal clock generation circuit 5000. This is because the voltage level applied to the gate of the MOS transistor is varied. Therefore, internal clock signal CLKin from internal clock generation circuit 5000 is desynchronized from external clock signal CLKex when periphery power supply voltage Vccp is varied, and it is no longer possible to operate internal circuitry properly in synchronization with the external clock signal. Data cannot be input or output at the desired timing, resulting in a problem that data cannot be transferred accurately.
The synchronous semiconductor memory device with a power down mode has clock enable signal CKE set to an inactive state of an L level in the power down mode. Here, internal clock generation circuit 5000 is inhibited of a clock generation operation. Internal clock generation circuit 5000 that has to operate speedily to generate a high speed clock signal includes a MOS (insulated gate type) transistor of a low threshold value voltage as the component. In this case, the sub threshold leakage current of the MOS transistor of the low threshold value increases in internal clock generation circuit 5000. Peripheral circuitry does not operate in the power down mode. Therefore, the leakage current with respect to periphery power supply voltage Vccp increases, so that current consumption in a power down mode cannot be reduced.
Generation of internal clock signal CLKin is inhibited in the power down mode. Internal clock signal CLKin must be speedily set to be in synchronization with the phase of external clock signal CLKex when exiting from the power down mode. When the number of stages of the train of inverters is increased and the unit delay time is reduced for the purpose of improving the accuracy of phase synchronization between external clock signal CLKex and internal clock signal CLKin, establishment of phase synchronization is time-consuming, and synchronization cannot be established speedily. Thus, there is a problem that the operation start timing cannot be advanced.
The problem of establishing phase synchronization is also encountered at the time of power on. When the power is turned on, internal clock signal CLKin is generated from internal clock generation circuit 5000 after initialization of internal circuitry. Phase synchronization between external clock signal CLKex and internal clock signal CLKin must be established speedily following stabilization of the power supply voltage. However, establishment of phase synchronization is time-consuming when the degree of accuracy of phase synchronization is set higher, similar to exiting from the power down mode. There is a problem that the synchronous semiconductor memory device cannot be operated at a fast timing after power-on.
In the conventional synchronous semiconductor memory device, there was a problem that an internal clock signal phase-locking with an external clock signal could not be generated stably and at high precision when the operating environment changes as at the stage of raising the power supply voltage after power-on or releasing the power down mode, and upon starting of operation of peripheral circuitry.